Low-thermal expansion circuit board and multilayer circuit board

ABSTRACT

A low-thermal expansion circuit board comprising an insulating layer made of an organic polymer having thereon a wiring conductor for bare chip mounting, wherein the wiring conductor is an iron-nickel-based alloy layer having a copper layer on at least one side thereof; and a low-thermal expansion multilayer circuit board having a plurality of the low-thermal expansion circuit boards via an adhesive layer, the adhesive layer having through-holes filled with solder to connect the circuits layers.

FIELD OF THE INVENTION

This invention relates to a low-thermal expansion circuit board and alow-thermal expansion multilayer circuit board for bare chip mountingwhich have a small thermal expansion coefficient and are thereforehighly reliable.

BACKGROUND OF THE INVENTION

With the recent tendencies for electronic equipment to have a smallersize and higher performance, it has been demanded for semiconductordevices constituting electronic equipment and printed circuit boards formounting the devices to have reduced size and thickness, higherperformance and higher reliability. To meet these demands, pin insertionmount is being displaced by surface mount, and, in recent years, asurface mount technology called bare chip mount has been under study, inwhich non-packaged (bare) semiconductor elements are directly mounted ona printed circuit board.

In bare chip mounting, however, because silicon chips having a thermalexpansion coefficient of 3 to 4 ppm/° C. are directly mounted on aprinted circuit board having a thermal expansion coefficient of 10 to 20ppm/° C., stress is developed due to the difference in thermal expansionto impair the reliability. The stress causes joint fracture in, forexample, flip chip bonding, which will lead to a faulty electricalconnection.

In order to relax the thermal stress, it has been practiced to fill thegap between a mounted semiconductor element and a printed circuit boardwith an adhesive called an underfilling material thereby to disperse thestress imposed to the joint. In order for the stress to be absorbed bythe printed circuit board itself, a multilayer printed circuit boardhaving shear stress-absorbing layers between circuit layers to provide astepwise gradation of thermal expansion coefficient in its thicknessdirection has been proposed (see JP-A-7-297560). However, reliabilityachieved by these techniques is still insufficient. It is indispensablefor securing further improved reliability to diminish the thermalexpansion coefficient of the printed circuit board itself.

In this connection, JP-A-61-212096 teaches a multilayer circuit boardcomprising an Fe—Ni alloy substrate having alternately formed thereoninsulating layers and wiring conductors and, if desired, having solderpads formed on the top layer thereof by photoetching, the substrate, theinsulating layers and the wiring conductors being united into anintegral laminate by pressure bonding under heat. The techniquedisclosed has the following disadvantages. Where copper is used as awiring conductor, it is difficult to reduce the thermal expansioncoefficient of the whole circuit board to the level of silicon becausethe elastic modulus of copper is far greater than that of a polyimideresin used as an insulating layer. The wiring conductor is formed bythin metallic film formation techniques, such as vacuum deposition andsputtering, which have low productivity and incurs increased cost.Formation of solder pads by deposition followed by photoetching requirescomplicated steps.

On the other hand, the increasing I/O pin count of semiconductors to bemounted has increased the necessity of laminating a plurality of circuitboards. A multilayer circuit board can be produced by a build up methodcomprising alternately building up, on one or both sides of a substrate,insulating layers of a photosensitive resin and conductor layers formedby plating or deposition. The build up method is disadvantageous in thatthe production process is complicated and involves many steps, the yieldis low, and much time is required.

JP-A-8-288649 proposes a method for producing a multilayer circuit boardcomprising forming protrusions of conductive paste by means of adispenser, etc. on the copper side of a single-sided copper-cladepoxy/glass laminate, pressing an adhesive sheet and copper foilthereto, and repeating these steps. This technique is unsatisfactory inreliability of electrical connection, connection resistivity, and thelike, and is hardly applicable to fine circuits. Further, it is atime-consuming method that the step of pressing must be repeated as manytimes as the number of the layers.

The inventors of the present invention have found that theabove-described problems associated with conventional techniques arechiefly caused by the extremely greater thermal expansion of the board,more specifically, the organic materials making up the insulating layer,such as an epoxy resin and a polyimide resin, and copper as a wiringmaterial, than that of semiconductor elements. Copper, which is commonlyused as a wiring conductor, has not only a large thermal expansioncoefficient but a large modulus of elasticity to increase the stress ofthermal expansion. Notwithstanding, copper is an excellent electricallyconductive material and has come to be indispensable as a wiringmaterial.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a low-thermal expansioncircuit board and a low-thermal expansion multilayer circuit board whichhave a small thermal expansion coefficient and are excellent inreliability.

The above object is accomplished by a low-thermal expansion circuitboard comprising an insulating layer made of an organic polymer havingthereon a wiring conductor for bare chip mounting, wherein the wiringconductor comprises an iron-nickel-based alloy layer having a copperlayer on at least one side thereof.

The object is also accomplished by a multilayer circuit board having aplurality of the above-described low-thermal expansion circuit boardslaminated integrally.

In the practice of the present invention, the multilayer circuit boardhas a plurality of double-sided circuit boards integrally laminated withan adhesive layer interposed between every adjacent circuit boards, theadhesive layer having through-holes at positions connecting the wiringconductors of the adjacent upper and lower double-sided circuit boards,and the through-holes containing a conductor made of solder by which thewiring conductors of the adjacent double-sided circuit boards areelectrically connected.

As a result of extensive study, the inventors have developed a highlyreliable low-thermal expansion circuit board by using a composite wiringmaterial composed of an iron-nickel-based alloy layer having a lowthermal expansion coefficient and a copper layer provided on at leastone side of the alloy layer. Copper wiring, which is the chief cause ofthe great thermal expansion of the circuit board, being directly formedon an iron-nickel-based alloy layer having a low thermal expansioncoefficient, the stress on thermal expansion of the wiring conductor canbe reduced. As a result, thermal expansion of the circuit board as awhole can be suppressed thereby to bring about improved reliability ofbonding after bare chip mounting.

The thermal expansion coefficient of the insulating layer, which isanother cause of the great thermal expansion of the circuit board, canbe reduced by using a polyimide resin prepared from pyromellitic aciddianhydride (hereinafter abbreviated as PMDA), m-tolidine (hereinafterabbreviated as m-TLD), and diaminodiphenyl ether (hereinafterabbreviated as DDE) which has a small thermal expansion coefficient. Thereliability of the circuit board can thus be enhanced further.

Where the insulating layer made of an organic polymer contains a coremade of an iron-nickel-based alloy or a ceramic material, the thermalexpansion coefficient of the insulating layer can further be reduced.

Laminating the low-thermal expansion circuit boards of the presentinvention provides a multilayer circuit board having the above-mentionedadvantages.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 through 6 each provide a cross sectional view showingpreparation of the low-thermal expansion circuit board according to thepresent invention.

FIG. 7 is a cross sectional view of an example of the low-thermalexpansion multilayer circuit board according to the present invention.

FIG. 8 is a cross sectional view of a three-layer sheet.

FIG. 9 is a cross sectional view of the three-layer sheet of FIG. 8 witha through-hole made therein.

FIG. 10 is a cross sectional view of the three-layer sheet of FIG. 9,with the through-hole being plated with copper.

FIG. 11 is a cross sectional view of the three-layer sheet of FIG. 10,with a circuit pattern formed on both sides thereof, i.e., a both-sidedcircuit board.

FIG. 12 is a cross sectional view of the double-sided circuit board ofFIG. 11 having an adhesive sheet temporarily adhered thereto.

FIG. 13 is a cross sectional view of the double-sided circuit board ofFIG. 12 with a solder bump formed in the through-hole of the adhesivesheet.

DETAILED DESCRIPTION OF THE INVENTION

The low-thermal expansion circuit board intended in the presentinvention means a circuit board having a thermal expansion coefficientlower than the thermal expansion coefficient of 10 to 20 ppm/° C.

The iron-nickel-based alloy which can be used in the invention includesnot only an iron-nickel binary alloy but iron-nickel alloys containingother elements such as cobalt as far as a low thermal expansioncoefficient is maintained. A preferred Ni content in the Fe—Ni binaryalloy ranges from 31 to 50% by weight. Out of this range, the alloy hasan increased thermal expansion coefficient, tending to have reducedreliability of bonding. The Fe—Ni—Co alloy includes those having anNi/Co/Fe weight ratio of 29/16/55, 32/8/60 and 36/4/60, which arecommercially available from Sumitomo Special Metals Co., Ltd. undertrade names of KV-2, KV-25 and Superinvar, respectively.

It is desirable that the total thickness of iron-nickel-based alloylayer(s) be 10% or more in the total thickness of the circuit board andbe greater than the total thickness of the copper layer(s). With thinneriron-nickel-based alloy layers, the circuit board will have an increasedthermal expansion coefficient and reduced reliability. The thickness ofthe circuit board is preferably 200 μm or smaller per wiring conductorfor achieving high-density mounting.

The organic polymer which can be used as an insulating layer is selectedappropriately from among those well-known in the art, such as phenolicresins, epoxy resins, polyester resins, polysulfone resins,polyether-imide resins, polyether ketone resins, and polyimide resins.If desired, the organic polymer material can be used in combination withpaper, glass cloth, glass mat, glass nonwoven fabric, Kevlar fiber, andthe like to form a composite insulating layer.

An insulating layer made of a polyimide resin prepared from PMDA, m-TLD,and DDE is preferred for its small thermal expansion coefficient. Whilepolyimide having a small thermal expansion coefficient can be obtainedwith the molar ratio of m-TLD and DDE to PMDA ranging from 0 to 100 mol%, the thermal expansion coefficient decreases with an increase of theproportion of m-TLD. In particular, when the proportion of m-TLD is 50to 100 mol %, the polyimide resin has a thermal expansion coefficient of10 ppm/° C. or less, and this is suitable to realize a circuit boardhaving a thermal expansion coefficient of 10 to 20 ppm/° C. or less.

The ceramic material which can be used as a core of the insulating layeris selected appropriately from those having a low thermal expansioncoefficient, such as alumina, mullite, cordierite, silicon carbide,silicon nitride, aluminum nitride, and zirconia.

Processes for producing the low-thermal expansion (multilayer) circuitboard according to the present invention will be illustrated byreferring to the accompanying drawings.

A circuit board precursor having a copper layer on one side thereof,i.e., a single-sided copper-clad laminate is prepared as follows. Afirst process shown in FIG. 1 comprises metallizing an organic polymerlayer (insulating layer) 1 by an appropriate combination of deposition,electroless plating, electroplating, etc. to form an iron-nickel-basedalloy layer 2 and a copper layer 3. A second process shown in FIGS. 2and 3 comprises forming a copper layer 6 on both sides of aniron-nickel-based alloy foil 5 by deposition, plating, cladding, etc. topreviously form a multilayer metal foil 7 as a wiring conductor andforming an organic polymer layer 1 on the surface of the multilayermetal foil 7 by, for example, casting. A third process shown in FIG. 4comprises forming an adhesive layer 8 on an organic polymer layer 1 by,for example, casting and heat and pressure bonding the multilayer metalfoil 7 shown in FIG. 2 onto the adhesive layer 8. A fourth process shownin FIG. 5 comprises providing the multilayer metal foil 7 shown in FIG.2 with an adhesive layer 8 by, for example, casting and heat andpressure bonding an organic polymer layer 1 onto the adhesive layer 8. Afifth process shown in FIG. 6 comprises preparing an organic polymerlayer 1, a multilayer metal foil 7 shown in FIG. 2, and an adhesivesheet 9 and heat and pressure bonding the organic polymer layer 1 andthe multilayer metal foil 7 via the adhesive sheet 9.

The adhesive used in the third to fifth processes as an adhesive layer 8or an adhesive sheet 9 includes thermosetting resins and thermoplasticresins, such as epoxy resins, phenolic resins, polyimide resins, andpolyamide resins.

A circuit board precursor having a copper layer on both sides thereof,i.e., a double-sided copper-clad laminate can be prepared in accordancewith the above-mentioned processes for preparing a single-sidedcopper-clad laminate. That is, a pair of single-sided copper-cladlaminates are joined to each other with a cast adhesive layer or anadhesive sheet therebetween. A double-sided copper-clad laminate canalso be prepared by laminating the multilayer metal foil 7 shown in FIG.2 on the organic polymer layer side of a single-sided copper-cladlaminate via an adhesive layer or an adhesive sheet. Where adouble-sided copper-clad laminate is prepared by using single-sidedcopper-clad laminates obtained by the third to fifth processes, it ispossible to conduct the two steps of heat and pressure bondingsimultaneously. As a modification of the first process, the organicpolymer layer 1 can be metallized on both sides thereof to prepare adouble-sided copper-clad laminate.

A copper-clad laminate having a core in its insulating layer can beprepared in the same manner as described above, except for replacing theorganic polymer layer 1 with a composite insulating layer prepared byheat and pressure bonding an organic polymer layer onto each side of acore via a cast adhesive layer or an adhesive sheet. The pressurebonding steps involved can be effected simultaneously. A copper-cladlaminate having a core in its insulating layer can be prepared by anyother combination of heat and pressure bonding, casting, andmetallizing.

A circuit pattern is formed on the single-sided or double-sidedcopper-clad laminate by a conventional subtractive process.Through-holes can be made through the double-sided copper-clad laminate.Where through-holes are made through a double-sided copper-clad laminatehaving an electrically conductive material (e.g., metal) as a core,electrical connections between the through-holes and the metallic coremust be avoided. That is, through-holes are previously made through ametallic core and, after a wiring conductor is provided on both sides ofthe composite insulating layer having the metallic core, through-holessmaller than those of the metallic core are made through the copper-cladlaminate concentrically with the through-holes of the metallic core.Further, after formation of the through-holes, both surfaces of thecircuit board and the inner wall of the through-holes may be plated withcopper.

The process for producing the multilayer circuit board of the inventionwill now be explained. As stated above, it is difficult with knownmultilayer circuit board structures and known processes for producingthem to satisfy all the demands for simplicity and economy of process,reliability on connections among circuit layers, and a reduced pitch.This is the very point the present invention aims at. In the presentinvention simplification of the laminating step and improvement ofeconomy are achieved by bonding a plurality of double-sided circuitboards under heat and pressure all at once unlike the conventional buildup method. Electrical connections among circuit layers are achieved by aconductor made of solder to secure higher reliability than conventionalconnections by conductive paste. The laminating can be carried out bytemporarily sticking an adhesive sheet having through-holes to adouble-sided circuit board at a right position, forming solder bumps inthe through-holes of the adhesive sheet, temporarily adhering anotherdouble-sided circuit board to the adhesive sheet at a right position,and finally bonding the laminate under heat and pressure into anintegral body.

The adhesive sheet suitably used in the preparation of the multilayercircuit board includes a sheet of thermosetting or thermoplastic resins,such as epoxy resins, phenolic resins, polyimide resins, and polyamideresins. Polyimide resins are preferred for their reliability. Where theadhesive sheet contains a thermosetting component, it should betemporarily adhered to the double-sided circuit board under controlledconditions so that curing may not proceed to such an extent to losere-adhesiveness in subsequent pressure bonding into a multilayer circuitboard. The thickness of the adhesive sheet is preferably 10 μm orgreater for securing workability and for leveling the unevenness of thecircuit and is preferably 200 μm or smaller for reducing the totalthickness of the multilayer circuit board. Through-holes can be made byknown techniques, such as drilling and punching.

Solder bumps can be formed by electroplating or printing with solderingpaste. Printing with soldering paste is preferred for its simplicity.The size of solder ball in the paste is 100 μm or smaller, preferably 50μm or smaller, still preferably 20 μm or smaller. The solder compositionis designed to have an appropriate melting point in accordance with thekind of the insulating layer and the necessity in mounting. The pressurebonding temperature may be either higher or lower than the melting pointof the solder as far as the adhesive sheet can manifest sufficientadhesiveness (500 g/cm or more). At temperatures higher than the meltingpoint of the solder, there is formed a metallic joint. Even attemperatures lower than the melting point of the solder, satisfactoryelectrical connections between circuit layers are secured.

FIG. 7 shows an embodiment of the multilayer circuit board of theinvention. Numeral 11 is a double-sided circuit board composed of aninsulating layer 12 made of a polyimide resin having formed on bothsides thereof a double metal foil (wiring conductor) 13, the doublemetal foil 13 being composed of an iron-nickel-based alloy foil 14 and acopper foil 15 as an outer layer. In this particular embodiment twodouble-sided circuit boards are laminated to provide a multilayercircuit board having 4 circuit layers. Each double-sided circuit board11 has a through-hole 11 a plated with copper to provide a platedthrough-hole 16 by which the double metal foils 13 on both sides areelectrically connected. The two double-sided circuit boards 11 arejoined via a polyimide adhesive layer 17 and electrically connected toeach other by a conductor 18 made of solder.

The multilayer circuit board of FIG. 7 is produced as follows. Apolyimide precursor varnish is applied to an iron-nickel-based alloyfoil 14, dried, and converted to a polyimide layer 12 to prepare atwo-layer sheet. Two two-layer sheets are pressure bonded under heat viaan adhesive sheet with the polyimide layers 12 facing each other toobtain a three-layer sheet 20 shown in FIG. 8. A through-hole 11 a isdrilled in the three-layer sheet 20 at a predetermined position, and thethrough-hole 11 a and the alloy foil 14 on both sides are plated withcopper by electroless plating and electroplating to obtain adouble-sided copper-clad laminate 21 shown in FIG. 10, in which numeral15 indicates a copper foil formed by copper plating. A circuit patternis made on the double metal foil 13 (composed of the alloy foil 14 andthe copper foil 15) on each side to prepare a double-sided circuit board11 shown in FIG. 11. An adhesive sheet 17 previously having athrough-hole 17 a made at a predetermined position is pressure bondedunder heat to one side of the double-sided circuit board 11 with thethrough-hole 17 a being positioned accurately as shown in FIG. 12. Theadhesive sheet 17 in FIG. 12 corresponds to the adhesive layer 17 inFIG. 7. The through-hole 17 a is filled with soldering paste by screenprinting through a metal mask to form a solder bump 18 as shown in FIG.13. A separately prepared double-sided circuit board 11 having athrough-hole at a predetermined position is then heat and pressurebonded to another double-sided circuit board 11 having the solder bump18 while positioning, thereby to obtain an integral 4-layer circuitboard shown in FIG. 7, in which the two double-sided circuit boards 11are electrically connected via the solder bump 18.

According to the above-described embodiment, the wiring conductor, i.e.,the double metal foil 13 made up of the iron-nickle-based alloy foil 14and the copper foil 15, has a small thermal expansion coefficient sothat the multilayer circuit board has excellent reliability. Moreover,the production process is simple and economical.

The present invention will now be illustrated in greater detail withreference to Examples, but it should be understood that the invention isnot deemed to be limited thereto.

EXAMPLE 1

A polyimide precursor varnish (a polyamic acid varnish prepared byreacting p-phenylenediamine and 3,3′,4,4′-biphenyltetracarboxylic aciddianhydride in N-methylpyrrolidone) was applied to a 10 μm-thick metalfoil made of a nickel-iron (42/58% by weight) alloy (thermal expansioncoefficient: 5 ppm/° C.), dried, and treated at 400° C. for 1 hour in anitrogen atmosphere to form a polyimide 10 μm thick. The resultingtwo-layer sheet was bonded to another two-layer sheet prepared similarlywith the polyimide layers facing each other via a 35 μm-thick polyimideadhesive sheet (SPB-035A, produced by Nippon Steel Chemical Co., Ltd.)at 200° C. while applying a pressure of 40 kg/cm² for 1 hour to preparea three-layer sheet. Copper was then deposited on the alloy foil on eachside of the three-layer sheet by electroless plating and electroplatingto a deposit thickness of 9 μm to prepare a double-sided copper-cladlaminate.

EXAMPLE 2

A double-sided copper-clad laminate was prepared in the same manner asin Example 1, except for changing the alloy composition of the metalfoil to nickel/iron=36/64% by weight (thermal expansion coefficient: 1.5ppm/° C.).

EXAMPLE 3

A double-sided copper-clad laminate was prepared in the same manner asin Example 1, except for changing the alloy composition of the metalfoil to nickel/cobalt/iron=32/8/60% by weight (thermal expansioncoefficient: 1.0 ppm/° C.).

EXAMPLE 4

A double-sided copper-clad laminate was prepared in the same manner asin Example 1, except that a polyimide adhesive sheet comprising PMDA,m-TLD and DDE at a molar ratio of 50/40/10 was used.

EXAMPLE 5

A double-sided copper-clad laminate was prepared in the same manner asin Example 1, except that the polyimide adhesive sheet was replaced witha 30 μm-thick nickel/iron (42/58% by weight) alloy layer having on bothsides thereof a 35 μm-thick polyimide adhesive sheet (SPB-035A).

EXAMPLE 6

A double-sided copper-clad laminate was prepared in the same manner asin Example 2, except that the polyimide adhesive sheet was replaced witha 50 μm-thick nickel/iron (36/64% by weight) alloy layer having on bothsides thereof a 35 μm-thick polyimide adhesive sheet (SPB-035A).

EXAMPLE 7

A double-sided copper-clad laminate was prepared in the same manner asin Example 1, except that the polyimide adhesive sheet was replaced witha 200 μm-thick aluminum nitride sheet (thermal expansion coefficient:4.3 ppm/° C.) having on both sides thereof a 35 μm-thick polyimideadhesive sheet (SPB-035A).

EXAMPLE 8

A double-sided copper-clad laminate having through-holes shown in FIG.10 was prepared in the same manner as in Example 1, except thatthrough-holes having a diameter of 0.2 mm were drilled through thethree-layer sheet (before copper plating) at predetermined positions(see FIG. 9). A circuit pattern was formed on the copper foil on eachside to prepare a double-sided circuit board shown in FIG. 11. Apolyimide adhesive sheet (SPB-035A) having through-holes of 0.2 mm indiameter previously made at predetermined positions was pressed onto oneside of the double-sided circuit board at 180° C. under 30 kg/cm² for 30minutes while positioning accurately as shown in FIG. 12. Solderingpaste (Sn8RA-3AMQ, produced by Nippon Sperior K.K.; melting point: 260°C.) was screen printed on the adhesive sheet through a metal mask tofill the through-holes with the soldering paste. After reflow at 290°C., the flux was washed away to form solder bumps as shown in FIG. 13.The resulting board with solder bumps was pressure bonded with anotherseparately prepared double-sided circuit board having through-holeswhile positioning at 200° C. and 30 kg/cm² for 1 hour to obtain a4-layered circuit board in which two double-sided circuit boards wereelectrically connected via the solder bumps.

Comparative Example 1

A polyimide precursor varnish (a polyamic acid varnish prepared byreacting p-phenylenediamine and 3,3′,4,4′-biphenyltetracarboxylic aciddianhydride in N-methylpyrrolidone) was applied to 18 μm-thick rolledcopper foil, dried, and treated at 400° C. for 1 hour in a nitrogenatmosphere to form a polyimide layer having a thickness of 10 μm. Theresulting two-layer sheet was adhered to another two-layer sheetprepared similarly with the polyimide layers facing each other via a 35μm-thick polyimide adhesive sheet (SPB-035A) at 200° C. under pressureof 40 kg/cm² for 1 hour to prepare a double-sided copper-clad laminate.

Comparative Example 2

A 4-layered circuit board was prepared in the same manner as in Example8, except that epoxy-silver paste was screen printed in place of thesoldering paste and heat-cured to form bumps.

The thermal expansion coefficient of the double-sided copper-cladlaminates prepared in Examples 1 to 7 and Comparative Example 1 wasmeasured in a temperature range of from room temperature (25° C.) up to200° C. The results obtained are shown in Table 1 below.

TABLE 1 Thermal Expansion Coefficient (ppm/° C.) Example 1 7.0 Example 24.2 Example 3 3.5 Example 4 5.8 Example 5 5.5 Example 6 3.0 Example 75.0 Comparative 17.0 Example 1

As is apparent from Table 1, the circuit boards according to the presentinvention have an extremely small thermal expansion coefficient, provingsuitable to bare chip mounting.

The multilayer circuit boards obtained in Example 8 and ComparativeExample 1 were subjected to a thermal cycle test to evaluate thereliability of the bump connection. As a result, 100% of the bump jointsin both samples showed satisfactory electrical conduction immediatelyafter heat and pressure bonding. After 500 thermal cycles of from 125°C.×30 minutes to −50° C.×30 minutes were given, 100% of the bump jointsin Example 8 achieved electrical conduction, whereas 10% of the bumpjoints in Comparative Example 2 showed faulty electrical connection. Themultilayer circuit board of the invention has now been proved superiorin reliability.

While in Example 8 filling of the through-holes 17 a of the adhesivesheet 17 with soldering paste was carried out by screen printing, it maybe effected by dispenser application or transfer application.

While the invention has been described in detail and with reference tospecific examples thereof, it will be apparent to one skilled in the artthat various changes and modifications can be made therein withoutdeparting from the spirit and scope thereof.

What is claimed is:
 1. A low-thermal expansion circuit board comprisingan insulating layer comprising an organic polymer having thereon awiring conductor for bare chip mounting, wherein said wiring conductoris an iron-nickel-based alloy layer having two opposing major surfaces,and a copper layer on at least one of said major surfaces.
 2. Thelow-thermal expansion circuit board according to claim 1, wherein saidinsulating layer is made of a polyimide resin prepared from pyromelliticacid dianhydride, m-tolidine, and diaminodiphenyl ether.
 3. Thelow-thermal expansion circuit board according to claim 1, wherein saidinsulating layer has a core made of an iron-nickel-based alloy or aceramic material.